Abstract
With the increase in memory-intensive applications, a memory-centric architecture has been proposed in which the central processing units (CPUs) access a pool of fabric-attached memory. This architecture eliminates the dependency of system components and provides benefits for achieving an independent upgrade cycle and fine-grained resource control. However, developing a memory-centric architecture requires new hardware and software for achieving the low-latency and high-bandwidth communication between the memory and the CPU. This paper presents a hardware prototype of a memory-centric architecture using Gen-Z, which is a new universal system interconnect optimized for ultralow latency and ultra-high bandwidth. The Gen-Z hardware prototype was designed according to the core specification 1.0a and implemented in two types of host interfaces. In this study, we measured the performance of the Gen-Z hardware prototype, i.e., the latency and throughput, and compared it with of the solid-state drive (SSD) and local memory. The experimental results indicated that the performance of remote memory access for a specific write request that utilizes the Gen-Z protocol was better than that of the SSD and local memory. Further, we discussed methods for improving the performance of the Gen-Z prototype.
Highlights
Memory capacity has become a bottleneck for datacenters because of the increased popularity of memory-intensive applications
To implement the Gen-Z host adapter that converts central processing units (CPUs) requests into the Gen-Z protocol, we used an SoC platform to implement it inside the chip and an field-programmable gate array (FPGA) to implement it outside the chip
We measured the performances of the remote memory access using the Gen-Z media controller and the performance of the local memory and solid-state drive (SSD)
Summary
Memory capacity has become a bottleneck for datacenters because of the increased popularity of memory-intensive applications. A traditional computer architecture adopts a processor-centric architecture wherein the memory and central processing unit (CPU) are coupled on a physical server The performance of such systems has increased with the CPU processing power. A CPU with an integrated memory controller (MC) accesses the remote memory through socket communication In this architecture, core-to-core latency occurs in the process of moving the data, and more CPU resources are needed to increase the memory capacity. In Contrast, in the memory-centric architecture shown, CPU nodes are connected directly to the shared memory pool via the Gen-Z fabric This allows the MC to decouple from the CPU, eliminating CPU and memory dependencies, which solves the problem of inefficient remote memory access, improves resource utilization efficiency, and provides operators with fine-grained resource control. The performance of the Gen-Z media controller for remote memory access was measured in terms of the latency and throughput, and the local memory and solid-state drive (SSD) were used to measure the relative performance
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