Hardware efficient narrow band FIR filter

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This paper presents a novel approach to implement a narrow band Finite Impulse Response (FIR) digital filter that requires less hardware than traditional FIR filter implementations. The hardware efficient Canonic Signed Digit (CSD) multiplier is used instead of the conventional multiplier to reduce the hardware. The digital filter has been initially designed using Simulink, DSP Blockset and has been tested for the required frequency response using Matlab. The FIR filter has been modeled and verified using Verilog HDL and is implemented using FPGA Xilinx 4000 technology. The use of the multistage multirate approach for the design of the FIR filter stages results in a hardware saving of about 80%.