Abstract
Discussed the hardware design and implementation of the image processing system with Virtex-XC5VSX95T as the algorithm processing chip. The large-capacity data storage chip XCF128X is selected to store the program flow. The user clock, DDR2 clock, SATA clock and other clock modules are designed. Designed LVDS and SATA as a high-speed data interface for image data transmission. Designed RS-422 as a communication interface for parameter, command and status data transmission. DDR2 memory modules and NAND Flash are as memory for image data caching. Dedicated voltage regulator chip is selected to meet the requirements of each module of the system for DC voltage. The test proves that the hardware design of the image processing system is correct and can realize the expected function.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
