Hardware design and implementation of digital payload data receiver of LAPAN-A2 satellite

Abstract

LAPAN A2 is the second-generation Indonesian micro satellite which designed and developed in Indonesia. This satellite was launched in September 2015 in India as piggy-back. Orbit of this satellite is circular and near equatorial with altitude approximately 650 km. This satellite carries digital payloads such as digital space camera, Automatic Identification System (AIS) for vessel traffic, and upgrade S-Band transmitter 3 Mbps. The digital payloads of LAPAN-A2 satellite data is downloaded in Rancabungur Ground Station, which is equipped with 11 meters antenna using S-Band frequency. The data generated from the satellite is in raw format. For ensuring this missions, it needs some hardware for receiving digital payload data of LAPAN-A2 satellite. This paper describes result of design, implementation and test from the hardware for receiving digital payload data of LAPAN-A2 Satellite. The hardware uses Morph-IC FPGA using software Quartus and microcontroller ATMega128 embedded using Basic compiler-AVR, then the design and layout of printed circuit board uses Eagle Software. From the result of the hardware functionality test of hardware payload data receiver system, the hardware is capable to pass the signal from transmitter S-band around 3Mbps and forwarded to PC by using communication serial with speed 6Mbps, and is able to download digital payload of LAPAN-A2 satellite either digital space camera or AIS data. The amount of received data depends on the height of elevation and attitude of the satellite.