Hardware Design and Analysis of Statistical Cipher Feedback Mode Using Serial Transfer

Abstract

In this paper, the hardware design of a recently proposed mode of operation for a block cipher, referred to as statistical cipher feedback (SCFB), is investigated. Specifically, we examine a structure which employs serial transfer from the plaintext queue to the ciphertext queue. SCFB mode is the hybrid of output feedback (OFB) mode and cipher feedback (CFB) mode that allows a block cipher to be configured as a self-synchronizing stream cipher. Consequently, SCFB mode feeds back ciphertext to the input of the block cipher similar to the conventional CFB mode, except that the feedback only occurs when the n bit sync-pattern is recognized thus making SCFB more efficient in its implementation than conventional CFB mode. An iterative based implementation of the advanced encryption standard (AES) is investigated and the relationship among three different clock domains associated with a serial transfer implementation is studied based on the synthesis results for various components of the system, as is the system efficiency. From simulations, an appropriate buffer size which minimizes queue overflow is selected for the design. The design is synthesized as an ASIC targeted to 0.18 CMOS standard cell technology. From the synthesis result, the throughput of the SCFB system is determined to be 100 Mbps. The total area of the SCFB system is approximately 41600 gates, of which 16900 is for AES.