Design of high throughput and area efficient advanced encryption system core

Abstract

A high speed security algorithm is always important for wired/wireless environment. The symmetric block cipher plays a major role in the bulk data encryption. AES is one of the best existing symmetric security algorithms to provide data security. AES (Advanced Encryption Standard) is a specification published in 2001 by the American National Institute of Standards and Technology, as FIPS 197. AES has the advantage of being implemented in both hardware and software. We present a hardware-efficient design increasing throughput for the AES algorithm using a high-speed parallel pipelined architecture. The pipelined architecture of the AES algorithm is used in order to increase the throughput of the algorithm and the key schedule algorithm of the AES encryption is also pipelined. The cores can be used in cipher feedback (CFB) mode, output feedback (OFB) mode, and counter (CTR) mode. The cipher blocks are then encrypted under some mode of operation. The advantage of these modes is only using encryption algorithm for both encryption and decryption. So the AES hardware may be reduced.