Hardware Description Beyond Register-Transfer Level Languages

Abstract

Prevalent hardware description languages (HDLs), e.g., Verilog and VHDL, employ register-transfer level (RTL) as their underlying programming model. One major downside of the RTL model is that it tightly couples design functionality with timing and device constraints. This coupling increases code complexity and yields code that is more verbose and less portable. High-level synthesis (HLS) tools decouple functionality from timing and design constraints by utilizing constructs from imperative programming languages. These constructs and their sequential semantics, however, impede construction of inherently parallel hardware and data scheduling, which is crucial in many design use-cases. In our work we present a novel dataflow hardware description abstraction layer as basis for hardware design and apply it to DFiant, a Scala-embedded HDL. DFiant leverages dataflow semantics along with modern software language features (e.g., inheritance, polymorphism) and classic HDL traits (e.g., bit-accuracy, input/output ports) to decouple functionality from implementation constraints. Therefore, DFiant designs are timing-agnostic and device-agnostic and can be automatically pipelined by the DFiant compiler to meet target performance requirements. With DFiant we demonstrate how dataflow HDL code can be substantially more portable and compact than its equivalent RTL code, yet without compromising its target design performance.