Hardware architecture design of HEVC entropy decoding

Abstract

As the latest generation of digital video coding standard, HEVC has technically optimized multiple modules such as related frame prediction, block processing and entropy coding in the frequency coding and decoding framework. However, flexible and efficient coding algorithms make the amount of calculation in the video decoding and reconstruction process increase dramatically. The energy efficiency of traditional processors is limited, and the decoding calculation process is difficult to meet the current needs of ultra-high-definition video playback. For the most important and time-consuming bitstream analysis and entropy decoding part of the HEVC decoding process, a new hardware architecture strategy is provided, which can effectively improve the HEVC decoding performance. In this paper, the designed data access module, bitstream analysis and entropy decoding unit are simulated and verified. Build an FPGA verification platform, and use the main tier standard test sequence to simulate and verify the designed hardware acceleration architecture. The experimental results show that the hardware architecture of bitstream analysis and entropy decoding designed in this paper can reach the functions and performance indicators specified by the HEVC standard Level-4 main tier, and the bitstream analysis acceleration effect is good. This thesis aims at the current HEVC decoding calculation characteristics, and through the design of hardware architecture verification, it provides new solutions and hardware architecture ideas for subsequent HEVC encoding and decoding performance optimization.