A High-speed Entropy Decoder For Hdt~

Abstract

An experimental VLSI entropy decoder which consists of a variable-length decoder and a run-length decoder will be presented. The experimental prototype chip has been simulated at 75 MHz. It demonstrates the feasibility of efficient real-time entropy decoding at HDTV rates. In many important applications such as image, video, and text compression, entropy coding is used to exploit the statistics of the input data to achieve lossless data compression. The most often used entropy coding techniques include variable-length coding [l] and run-length coding [2]. In variable-length coding, shorter codewords are assigned to more probable source symbols so that the average bit-rate is reduced. In run-length coding, consecutive zeros are represented by the zero-run-length so that the number of samples is reduced. Many proposed video standards have included the variable-length coding and run-length coding as standard techniques in their coding algorithms [3-51. The variable-length nature of the codewords, however, introduces difficulties for high-speed entropy decoding (e.g. for HDTV rates at 50 MHz and above). After the concatenation of variable-length codewords, the word-boundary can not be determined explicitly before decoding. The decoder has to decode a codeword and its length, and shift the data-stream according to the decoded length before it can start decoding the next codeword. These are recursive operations that can not be pipelined. Besides this inherent feedback-loop, the variable-length decoder (VLD) also needs to handle the feedback from the run-length decoder (RLD) and the external buffer memory, and takes special actions when transmission errors occur In this paper, an experimental research prototype entropy decoder VLSI will be discussed. The experimental prototype chip includes a VLD and RLD. Since the RLD is relatively easy to implement, we will focus our discussions on the VLD. The maximum codelength is 16. The output of the VLD is 8-bit wide with the Most-Significant-Bit (MSB) indicating whether it is a run-length code. The output of the RLD is 7-bit wide. The chip has been simulated to operate at 75 MHz. At this clockrate, the VLD decodes 75 M samples/s and handles a maximum input rate of 1.2 Gb/s with a constant output rate of 600 Mb/s. The organization of the paper is as follows. In Section 2, the overall entropy decoder chip is described. In Section 3, the architecture and operation of the VLD is discussed. The implementation of the entropy decoder is discussed in Section 4. Some suggestions for even higher-speed implementations are discussed in Section 5. Finally, a conclusion is presented in Section 6.