Hardware-and-memory-sharing architecture of deblocking filter for VP8 and H.264/AVC

Abstract

In this paper, a hardware sharing architecture is proposed to support multi-standards--VP8 and H.264/AVC. To achieve a common architecture, the deblocking filters of VP8 and H.264/AVC are reorganized, and the lossless sharing architecture (RO-DBK) is obtained. For the lossy application such as low-resolution display devices, the modified coefficients to derive a highly sharing architecture (LC-DBK) are further adapted. The experimental results show that the PSNR only drops 0.36% on average for LC-DBK. These two proposed architectures save 74.2% and 80.2% arithmetic logic units, respectively. To further reduce memory usage, we propose a new VLSI architecture. In this VLSI architecture, the deblocking filter and the interpolation result of motion compensation and inverse transform share the same SRAM. To achieve this, a rearranged filtering order is also proposed. This design only uses 32 bytes transpose buffer without any SRAM usage. To reach real-time processing, a 3-staged pipeline scheduling is also proposed. The proposed design is implemented within 0.18 μm process. The working frequency is 100 MHz and the overall gate count is 3.9K.