Hard-Switch Stressing of Vertical-Channel Implanted-Gate SiC JFETs

Abstract

A requirement for the commercialization of power SiC transistors is their long-term reliable operation under the hard-switching conditions encountered in the field. Normally ON 1200-V vertical-channel implanted-gate SiC JFETs, designed for high-power bidirectional (four-quadrant) solid-state-circuit-breaker applications, were repetitively hard switched from a 150-V blocking state to an on-state current in excess of eight times the JFET's 250-W/cm2 rated current. The JFETs were fabricated in seven photolithographic levels with a single masked ion implantation forming the p+ gates and guard rings and no epitaxial regrowth. The hard-switch testing was performed using an RLC circuit capable of currents in excess of 200 A with a rise time of 150 A/ μs. In this circuit, energy initially stored in the capacitor is discharged to the resistor through the JFET under test. The JFET hard-switch stressing included 1000 shots at each temperature of 25 °C, 50 °C, 100 °C, and 150 °C and at each repetition rate of 1, 5, 10, and 100 Hz for a total of 16 000 shots. Peak energies and powers dissipated by the JFET were 7.5 mJ and 9 kW, respectively. JFET conduction and blocking-voltage characteristics remain unchanged after 16 000 pulsed hard-switching events, which is indicative of reliable operation and excellent JFET suitability for nondegrading repeated bidirectional high surge-current fault isolation.