Handshake-wave combined approach with runtime reconfiguration for designing a low latency asynchronous FIFO

Abstract

In this paper, a novel design scheme combining a handshake protocol and wave pipeline is proposed to improve latency performance of an asynchronous linear FIFO. The stage control of the proposed FIFO can be reconfigured dynamically to be one of two different operating styles, waving or handshaking, according to the status of data flow in the FIFO. The use of wave pipelining in a control and a datapath can eliminate delays of handshaking circuits and latching data respectively. The proposed circuits have been designed with 0.25 /spl mu/m, 2.5 V CMOS process technology and simulated using HSPICE. Preliminary results show about two times improvement on latency performance over a state-of-art linear FIFO circuit while retaining throughput and a simple linear structure.