Scaling up of wave pipelines

Abstract

Wave pipelining is a technique of arranging synchronous logic circuits in a pipeline fashion based on delay balancing that allows clocking rate higher than that of well-known regular pipelining. In order to scale up wave-pipelined circuits in the trend of VLSI development toward tighter integration, firstly we investigate scale-dependent characteristics of those circuits with simple structure. It is shown that larger scale is more favorable in view of pipeline degree and vector-execution time. Secondly we explore multifunctional wave pipelines with considerable scales and complicated structures. A fully wave-pipelined structure is recommended to multifunctional circuits regarding software overheads and areas. Thirdly, we show the standard cell synthesis of a fully wave-pipelined scalar processing unit to demonstrate the practicality of wave pipelining multifunctional random logic circuits. By using 0.5-/spl mu/m CMOS technology, a scalar processing unit is implemented in a 2.3-mm/spl times/2.3-mm chip whose clock speed is estimated to be 1 GHz from circuit level simulation.