Abstract
Key process and device modeling issues are described that were addressed during development and optimization of a high performance NPN transistor built in a 0.5 /spl mu/m BiCMOS technology for digital and mixed signal applications. Process issues included the deconvolution of shallow SIMS emitter profiles to obtain a more accurate picture of the underlying intrinsic device, detailed modeling of grain growth and diffusion in the dual polysilicon structure, and modeling of lateral diffusion of the link base. Extensive RSM device modeling was used to simulate trends in device characteristics resulting from variations in device structure. This work resulted in a device with improved overall performance.
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