Abstract
An optimization principle for ferroelectric FET (FeFET), centered around charge matching between the ferroelectric and its underlying semiconductor, is theoretically investigated. This letter shows that, by properly reducing the ferroelectric polarization charge and its background dielectric constant, charge matching can be improved to enable simultaneously: i) reduction of the interlayer and semiconductor electric fields during programming, reading, and retention, leading to prolonged endurance and retention; ii) improvement of the memory window; and iii) suppression of device-to-device variations by affording full polarization switching. These attributes provide an incentive for the presentation of the proposed guidelines for FeFET optimization as detailed in this letter.
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