Guest editorial: special issue on on-chip inductance in high-speed integrated circuits

Abstract

HE appropriate interconnect model has changed several times over the past two decades due to aggressive technology scaling. New, more accurate interconnect models were introduced when parasitic effects that were negligible in earlier technologies, could no longer be ignored. Currently, RC models are used to analyze high resistance nets while capacitive models are used for less resistive interconnects. However, on-chip inductance is becoming increasingly important since integrated circuits now operate at frequencies where the inductive impedance of thick wide wires is comparable to wire resistance and line lengths are long enough, relative to signal rise times, for transmission line behavior to become significant. Furthermore, this trend shows every indication of spreading beyond the relatively few lines it now affects. Operating frequencies that have increased dramatically over the past decade, are expected to maintain the same rate of increase over the next decade approaching 10 GHz by the year 2012. The use of thick upper level metals, large die sizes, and low resistance copper interconnect—already used in many commercial CMOS technologies, will likewise continue. Finally, because large die sizes enable more system integration, the use of long thick wide wires, once largely devoted to global clock distribution networks, will spread to critical data-buses and control lines. This special issue deals with the design and analysis of integrated circuits including parasitic on-chip inductance. It does not deal with intentionally designed structures like the spiral inductors used in RF circuits and LC tank oscillators. As evidence that the subject material is still under investigation, the papers in this special issue do not present a unified approach to modeling parasitic inductance. The most notable difference centers around the use of 2-D (or loop inductance) models versus more general 3-D inductance models, and at the center of this debate is the question of current loops formed by return currents. The 3-D model advocates take the position that the return current paths are fundamentally unknown and present sophisticated analysis methods to cope with the increased complexity of 3-D models. The 2-D advocates insist that the return currents are equal and opposite to the interconnect currents and can therefore, employ simpler models. While this debate is apparent in the second paper which favors 2-D models and the third, fourth, and sixth papers which favor 3-D models, several other papers also imply a preference by presenting analytical methods that are suitable to 2-D models only. The paper summary below highlights when notable, the authors stated or implied preference to 2-D or 3-D models. In the first paper, Ismail presents several analytical methods for including inductive effects in both timing and noise analysis. The analytical models he presents are only applicable to