Ground bounce noise minimization using Multi-VDD Level Converter

Abstract

In Multi-VDD system, Level Converter (LC) is used to convert one voltage level to another level (i.e. high to low and low to high). Power gating is an approach to reduce the dynamic and standby leakage in the present day System on Chip (SoC) design. As we go lower down the technology node problem of ground bouncing starts to dominate the system. It leads to various kinds of errors especially the functional ones. Here, we are using low to high level converter, whose output is used as an input signal to the sleep transistor (ST) in power gating technique to reduce the leakage current and Ground Bounce in circuit. This is achieved by reduction in the Virtual Ground (VGND) node voltage. Using this LC, VGND is maintained below the threshold voltage of ST, so that ST does not go in the saturation region. When ST is transitioning from sleep mode to active mode, small discharge current flows through the VGND node and thus limiting the bouncing. Using this technique, we have achieved 83% and 92% reduction in ground bounce and transition energy respectively as compared to conventional power gating technique. Simulations are carried out using 32-bit Ripple Carry Adder as low Vth logic circuit in Cadence Virtuoso simulation environment and UMC 0.18μm technology.