A novel ground bounce reduction technique using four step power gating

Abstract

The power gating is a technique to reduce leakage power in standby mode by using Sleep switch. In power gating, the circuit suffers the ground bouncing due to the switching of the Sleep Transistor from standby mode to active mode. In this paper, we have presented a four step power gating technique for further reducing the Ground/Power bouncing. This technique not only controls the bouncing but also controls the wake-up time and transition energy overheads in transition period. To control the wakeup time, pre-boosting and post-boosting current technique is applied by using two MOS transistors, limiting the discharge current and voltage swing in noise limiting stage. Application of proposed technique reduces 73% and 20% bounce noise as compared to conventional power gating and three step power gating techniques respectively. Simulations are carried out using 4-bit Ripple Carry Adder as low V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> logic circuit in Cadence Virtuoso simulation environment and UMC 0.18μm technology.