Abstract

The Josephson balanced comparator, a decision-making circuit comprising two Josephson junctions (JJs) connected in series from a clocking perspective and in parallel for the current to be measured, is ubiquitous in single flux quantum (SFQ) logic. Its noise properties are crucial for the performance of logic devices. The characteristics of the balanced comparator can also be used to monitor fab process and design implementation as an indicator for excess noise, overheating, linearity, dynamic effects, etc. We designed several test structures to measure gray zone of various comparators fabricated in different nodes of process at MIT-LL. We used digital circuitry to measure comparator characteristics at low frequencies and an analog testbed to perform high frequency characterization. Experimental results for gray zone of comparators designed for fabrication nodes with different current densities, sheet resistances, critical damping are presented and studied as a function of clock frequency.

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