Abstract
This paper addresses the problem of worst-case timing analysis of heterogeneous wormhole NoCs, i.e., routers with different buffer sizes and transmission speeds, when consecutive-packet queuing (CPQ) occurs. The latter means that there are several consecutive packets of one flow queuing in the network. This scenario happens in the case of bursty traffic but also for non-schedulable traffic. Conducting such an analysis is known to be a challenging issue due to the sophisticated congestion patterns when enabling backpressure mechanisms. We tackle this problem through extending the applicability domain of our previous work for computing maximum delay bounds using Network Calculus, called Buffer-aware worst-case Timing Analysis (BATA). We propose a new Graph-based approach to improve the analysis of indirect blocking due to backpressure, while capturing the CPQ effect and keeping the information about dependencies between flows. Furthermore, the introduced approach improves the computation of indirect-blocking delay bounds in terms of complexity and ensures the safety of these bounds even for nonschedulable traffic. We provide further insights into the tightness and complexity issues of worst-case delay bounds yielded by the extended BATA with the Graph-based approach, denoted G-BATA. Our assessments show that the complexity has decreased by up to 100 times while offering an average tightness ratio of 71%, with reference to the basic BATA. Finally, we evaluate the yielded improvements with G-BATA for a realistic use case against a recent state-of-the-art approach. This evaluation shows the applicability of GBATA under more general assumptions and the impact of such a feature on the tightness and computation time
Highlights
Networks-on-chip (NoC) have become the standard interconnect for manycore architectures because of their high throughput and low latency capabilities
We proposed a new approach, G-Buffer-aware worst-case Timing Analysis (BATA), improving the indirect blocking analysis based on dependency graphs to capture interference patterns involving consecutive-packet queuing (CPQ)
We evaluated our approach on several aspects: (i) we studied the sensitivity of the model to input parameters such as router buffer size, flow rate, and packet length
Summary
Networks-on-chip (NoC) have become the standard interconnect for manycore architectures because of their high throughput and low latency capabilities. BATA is applicable for a large panel of wormhole NoCs: (i) routers implement a fixed priority arbitration of VCs; (ii) a VC can be assigned to an arbitrary number of traffic classes with different priority levels (VC sharing); (iii) each traffic class may contain an arbitrary number of flows (priority sharing) This approach, along with many other stateof-the-art approaches in timing analysis of NoCs taking backpressure into account, considers only Constant Bit Rate (CBR) traffic, i.e. one fixed-length packet within a minimum inter-arrival time. There is an additional packet of flow 2, C, right behind B It was granted the use of output port East of R3 and is waiting at R4 for the input buffer of its path to be available.
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