Abstract
Non-destructive golden-free detection of recycled/counterfeit integrated circuits (ICs) is the focus of this paper. This is achieved by estimating the functional/operational age of the IC. The age estimation method is based on exploiting short-term aging effects in advanced transistor technologies to induce bit errors at the IC’s output. Gate-level simulations are used to capture the impact of workload on short-term aging. In advanced technology nodes including bulk CMOS at 45 nm or below and FinFET, combining transistor aging with ultra-fast voltage scaling magnifies effects of aging-induced degradation at high voltage when voltage scales to a lower level, causing short-term aging-based timing violations. These timing violations create bit errors at IC outputs. We employ the bit error patterns to build a machine learning (ML) based non-linear regression model to estimate the IC’s age. Our study confirms that short-term aging-induced output bit error patterns can be used to estimate long-term age of an IC. If the IC’s age is beyond a pre-defined threshold, it can be marked as recycled. Although this paper considers FinFET technology, the method applies to bulk CMOS advanced nodes at 45nm or below. We model IC-to-IC variations taking into account voltage scaling. We demonstrate the approach on two cryptographic ICs and the method accurately estimates the long-term age of an IC, facilitating recycled IC detection.
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More From: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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