Abstract

The global VLSI (very large scale integration) systems design cycle is briefly discussed below with respect to relationships between design stages, bottlenecks, and current open issues for design automation (DA). The design cycle involves moving from an abstract design specification to gradually a more detailed single or multichip design that can be tested and fabricated. The VLSI design stages are very interdependent and therefore it is important to outline the purpose of each stage before one can address the problems of high level synthesis. Area, power, speed, timing issues, input and output pin limitations, testability, and many other criteria are important in the design process. Interfaces to other complex processes, design complexity with respect to implementation technologies and testability will also be discussed. In addition, an understanding of the current computer aided-design (CAD) bottlenecks and open issues will further emphasize the importance and impact of high level architectural synthesis (the focus of this text) on the VLSI design cycle.

Full Text
Paper version not known

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.