Glitch-less hardware implementation of block ciphers based on an efficient glitch filter

Abstract

In this paper, we present a glitch-less hardware structure based on a glitch filter for the implementation of the block ciphers. The glitch filter circuit is used to build a glitch-free arbitrary binary signal at full clock speed based on both positive and negative clock edges. In this technique, the desired signal is constructed by combining two signals whose individual frequencies are one-half that of the original signal. From the hardware point of view, the circuit does not employ delay blocks that depend on routing delays. Therefore, this property is suitable for use in both VLSI- and FPGA-based implementations. The glitch filter stops pulses of narrow width while allowing the passage of pulses of larger width. The circuit removes chatter and extraneous noise in hardware structures of the cryptosystem without affecting the output signal. The glitch filter can play both roles of the register for save of data and also glitch remover. In this case, the area overhead for the glitch-less structure is negligible. Therefore, we achieving a good trade-off between glitch-less and area overhead which is essential for an efficient design. The delay and area consumption of the different block ciphers such as PRESENT, HIGHT, and SPECK based on glitch filter circuit are achieved in 180 nm CMOS technology. The results show that the proposed structures have an acceptable area and time complexities compared to the original structures.