Germanium PIN detector on silicon grown by Sb surfactant-assisted epitaxy

Abstract

High speed optical detectors compatible with Si complementary metal oxide semiconductor (CMOS) technology are required to advance local area networking (LAN), board to board, and chip to chip communications. Ge has suitable properties to produce appreciable response under illumination at 1.55 micron wavelength, but has a substantial amount of lattice mismatch (~4%) to Si. Two methods have been employed previously to alleviate strain between these two materials; thick, graded buffer layers [1] and thin, very low temperature epitaxial growth layers [2] to create a virtual substrate (VS) of Ge on Si. These methods have been used to produce Ge PIN diodes with dark current densities at one volt of 40 A/cm2 and 100 mA/cm2 respectively. [3, 4] The photoresponse for these PIN devices are 109 mA/W and 20 mA/W. Each technique has disadvantages. The graded buffer layer technique employs a VS thickness of several microns to achieve appreciable strain relief. The very low temperature epitaxy technique has a narrow thermal process window (~ 50 °C) around 200 °C. In the current work, Ge PIN diodes were fabricated on Ge VS on Si substrates using Sb surfactant-assisted growth. Previous studies have shown this method minimizes the threading dislocations [5] and results in a smooth surface. A potential concern is the unintentional doping by the Sb surfactant that continues to segregate. In the PIN devices this may be acceptable since the residual doping can be used as the n electrical contacts or used as a technique to electrically isolate the p contact from the substrate.