Abstract
Ge-MOS devices (EOT /spl sim/7.5 /spl Aring/, J/sub g/ /spl sim/ 10/sup -3/ A/cm/sup 2/) are fabricated on both n- & p-type Ge-substrates, using novel surface passivation and TaN/HfO/sub 2/ gate stack. Results show that the plasma-PH/sub 3/ treatment and thin AlN layer at HfO/sub 2//Ge interface are effective to suppress the GeO formation, which is mainly formed during HfO/sub 2/ deposition, and prevent Ge out-diffusion, resulting in improved C-V characteristics for n-MOS device with extremely low leakage. Thermal stability study of TaN/HfO/sub 2//Ge gate stack shows that low leakage with thin EOT can be obtained after post-anneal at 500 /spl deg/C and degradation is observed above 600 /spl deg/C. It is also observed that good Ge n/sup +/-p and p/sup -/-n diode characteristics are achieved by S/D activation at 500 /spl deg/C and 400/spl deg/C, respectively. Both p- & n-MOSFETs are fabricated by conventional self aligned process with maximum temperature of 500 /spl deg/C. Compared to reported Si-MOSFETs, the mobility enhancement of 1.6X for hole and 1.8X for electron is observed with Ge-MOSFETs.
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