Enhanced Ge MOS Device Performance Through a Novel Post-gate CF4-plasma Treatment Process

Abstract

A post-gate CF4-plasma treatment process is proposed and demonstrated on Ge MOS devices and the effects of F incorporation have been extensively studied on both high-k/Ge gate stacks without any surface passivation and with Si surface passivation. Our results show that: (1) F is effectively introduced into the gate stack by CF4 treatment and segregates near high-k/Ge interface; (2) Electrical characteristics like Dit, gate leakage, C-V hysteresis and breakdown voltage are improved after F incorporation; (3) Post-gate CF4 treatment is also compatible with pre-gate surface passivation, and it can further enhance the device performance. By combining Si surface passivation and post-gate CF4 treatment, interface quality has been greatly improved for high-k/Ge gate stack and a high peak hole mobility of 376 cm2/V⋅s has been achieved for Ge pMOSFETs