Germanium nMOSFETs with GeO2 Passivation and n+/p Junctions Formed by Spin-On Dopants

Abstract

Germanium is an attractive channel material for future CMOS scaling because of its higher electron (~2x) and hole (~4x) mobilities compared to Si. While high-performance Ge pFETs have been consistently demonstrated, Ge nFETs continue to show empirical electron mobilities inferior to that of Si. Two of the presumed culprits for this behavior are the high density of interface states (Dit) near the conduction band edge and the poor activation of n-type dopants. In this work, Ge devices are fabricated with a gate stack consisting of an Al2O3 high-k dielectric with GeO2 interfacial passivation layer and a TaN metal gate. Diodes and nFETs contain n+ layers formed via a (SOD), using Ni source and drain contacts (Fig 1). Recent research by several groups has shown that a promising way to reduce Dit is to introduce a thin GeO2 passivation layer between the channel and the high-k dielectric [1-2]. In this work we utilize a rapid thermal oxidation (RTO) generated GeO2 layer we previously demonstrated [3]. A gate-last approach is used for FET fabrication, as temperatures greater than 400 C will damage the GeO2 passivation and cause degraded C-V inversion and ID-VG characteristics (Fig 2). The second issue plaguing Ge nFETs is the presence of poor n+/p junctions. Low dopant activation and high n-type dopant diffusivity cause high series resistance which reduces performance. Our n+/p junctions are fabricated by a spin-on layer of P-containing SOD (from Filmtronics, Inc.) which is followed by a rapid thermal drive-in [4]. Anneal conditions are optimized from 650-750 C (for 10 s) and yield peak activation concentrations of more than 7x1019 cm-3 (Fig 3). The method is similar in nature to solid source diffusion, but offers the ability to quickly spin-coat the surface and benefits from a reduced thermal budget. Spin-on dopant based n+/p diodes (~0.07 ohm-cm substrate) exhibit higher Ion/Ioff ratios (~106), reduced reverse diode leakage (~2 orders lower) and a superior ideality factor (n ~ 1.03 vs. 1.45) compared to their ion-implanted counterparts (1x1015 cm-2, 30 keV, 500 C, 30 s anneal) (Fig 4). This process avoids implantation-induced damage, and the low ideality factor for SOD devices corroborates a lower defect density in the junction. Germanium nFETs fabricated with SOD also show improved performance relative to implanted samples. As shown in Fig. 5, the SOD nFETs show high Ion/Ioff ratios (~104) with high drive current (~12uA/um) and low subthreshold slope (~110 mV/dec.). In addition, the SOD samples show less pronounced GIDL and display ~20% enhancement in electron mobility after series resistance correction (Fig. 6). The ultimate goal for Ge FETs will be to replace Si, and epitaxial Ge on Si is one such way to realize the higher performance Ge offers while maintaining integration with conventional Si processes. Unfortunately, the large (~4%) lattice mismatch causes defects at the interface during epitaxy and results in rough and electrically defective surfaces. To avoid this, our group uses CVD Ge1-xCx (with x~1%), which drastically reduces the defect density and yields low RMS roughness without affecting device performance [5]. Work on SOD-formed n+/p junctions in both GeC and GeC-on-insulator devices is currently ongoing and will be presented alongside the Ge data.