Abstract
Boolean function manipulation is an important component of many logic synthesis algorithms including logic optimization and logic verification of combinational and sequential circuits. Digital integrated circuits, often represented as Boolean functions, can be best-manipulated graphically in the form of Binary Decision Diagrams (BDD). Reduced-ordered binary decision diagrams (ROBDDs) are data structures for representation and manipulation of Boolean functions. The variable ordering largely influences the size of the BDD, varying from linear to exponential. In this paper, an evolutionary algorithm named genetic algorithm has been proposed for minimization of shared ordered BDDs by finding the optimal input variable ordering that aims to minimize the node count using Genetic algorithm. The proposed algorithm gives upto 79% less nodes for LGSynth93 Benchmark Circuits.
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