Generation of optimised fault lists for simulation of analogue circuits and test programs

Abstract

The definition of a universally acceptable analogue fault model has been a major obstacle to the acceptance, by industry, of any of the new test and testability techniques that have been proposed for analogue and mixed-signal circuits. This is largely because analogue faults are difficult to model and very time consuming to simulate. Previous independent research has demonstrated how inductive fault analysis can be used to reduce the size of a fault set and how circuit sensitivity analysis can be employed to ascertain what constitutes a fault for each circuit component. The authors combine these two principles by first employing an inductive fault analysis to eliminate faults which are unlikely to occur from the fault set, and then employing a circuit sensitivity analysis to eliminate from the remaining set ‘faults’ which have no effect on circuit functionality. As a result, fault simulation becomes a significantly less onerous task and the evaluation and comparison of test programs and techniques can be achieved much more conveniently.