Generation of Fast Target Processor Code from High Level Controller Descriptions

Abstract

Abstract This paper addresses the translation of a multivariable controller description into code for fast target processors, particularly digital signal processors. The feasability and viability of automatic generation of optimal machine code from multivariable controller data (system matrices) have already been demonstrated in the past. Increasing control task complexity, as well as the necessity of getting as much target processor independence as possible, now leads to the definition of DSPL, a digital systems programming language. Translation into machine code for (signal) processors is performed by DSPL-compilers written specifically for those processors, exploiting the various special signal processing features found there. Code optimization can be directed to space or time for individual blocks of the control task, and the best code construct will be automatically selected according to global objectives.