Abstract
Hardware Description Languages at the RT level may be used as the front end of a VLSI Design Automation system. A hardware compiler will, therefore, be needed for the translation of RTL descriptions into proper form of hardware. An AHPL based hardware generation program with dynamic MOS target will be described here. The emphasis will be on the hardware compiler and MOS two phase implementation of AHPL constructs. The compiler's output may be used for gate or circuit level testing of the input AHPL description.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
