GDI implementation of low power modified booth multiplier

Abstract

In digital signal processing the speed of the processor is dependent on the processing speed of a multiplier used in it, which affects total processing of a circuit. Hence, when a normal multipliers are used they consumes most of the power also gives rise to a delay. So to overcome this problems the high speed digital multiplier used nowadays. This paper introduced a low power booth multiplier, which work on a partial product, shifted approximately and addition. For the design of low power circuit the Gate Diffusion Input technique used. This technique plays a key role in the low power reduction technique. The speed booth multiplier is depending upon the partial product. As the booth multiplier cuts the required partial product into half so the speed of partial product increase's. The booth multiplier consists of a three section encoder, partial product generation unit and adder circuit. Implementation of a booth multiplier takes place using a cadence virtuoso. The result obtained is in term of average power and is compared with the performance of GDI to static CMOS technique at 45nm technology. The voltage used for the circuit varies from 0.1 to 0.7 volts.