Gated twin-bit silicon–oxide–nitride–oxide–silicon NAND flash memory for high-density nonvolatile memory

Abstract

In this paper, we report the fabrication and analysis of the gated twin-bit NAND flash memory with a nitride charge-trapping layer. This device is based on the recessed channel structure, and it has an additional cut-off gate that enables 2-bit operation. Therefore, the density of the array can be doubled without any difficulty in patterning. The fabrication method for gated twin-bit (GTB) silicon–oxide–nitride–oxide–silicon (SONOS) memories and their electrical characteristics are described in this paper. Program/erase characteristics are observed and the 2-bit operation is verified by the forward–reverse reading scheme.