Gate tunneling current model of strained Si for scaled NMOSFET

Abstract

For scaled MOSFET devices, normal operation of devices is seriously affected due to static gate tunneling leakage currents with ultra-thin gate oxide of MOSFET, and the novel MOSFET devices based on strained Si are similar to bulk Si devices in the effects. To illustrate the impacts of gate leakage current on performances of novel strained Si devices, a theoretical gate tunneling currents predicting model by integral approach following the analyses of quasi-two-dimension surface potential is presented in this paper, and on the basis of theoretical model, performances of NMOSFET devices were quantitatively studied in detail using ISE simulator including different gate voltage and gate oxide thickness. The experiments show that simulation results well agree with theoretical analysis, and the theory and experimental data will contribute to future VLSI circuit design.