Gate oxide degradation during polysilicon etching in a parallel-plate plasma-type etcher

Abstract

Gate oxide degradation by transient surge current has been tested during polysilicon etching in a parallel‐plate plasma‐type etcher. To reduce the transient surge current, rf power is removed gradually at a rate of 50 W/s after 50% overetch. Breakdown voltage distribution measured at a metal–oxide–semiconductor capacitor array structure with gate edges is improved considerably by the ramping down of rf power. This clearly indicates that the transient surge current can cause charge damage to some extent even in a plasma‐type etcher. Gate oxide recovery during the interpolyoxide deposition is also discussed.