Gate oxide damage from polysilicon etching

Abstract

Damage to thin gate oxides from etching of polysilicon gates was studied using gate oxide breakdown histograms and time-dependent dielectric breakdown measurements. The effect of various polysilicon etch parameters was investigated in a radio frequency (rf) triode etcher. Increasing rf power caused a substantial increase in damage. Reducing bias at constant power also resulted in an increase in damage, indicating that ion energy is not the only cause of damage. Area, isolation edge, and source/drain edge contributions to gate oxide defect densities were calculated as a function of rf power during polysilicon etch. As rf power was increased, the area contribution increased the most, indicating that gate oxide damage from polysilicon etching is not an edge phenomenon but a surface phenomenon. The effect of gate oxide thickness was investigated. Damage increased significantly as gate oxide thickness was reduced. Finally, the rf triode etcher was compared with a microwave electron cyclotron resonance (ECR) etcher. The ECR etcher caused fewer damaged capacitors, but some modifications to the triode etch process (such as lower rf power or pure chlorine chemistry) produced fewer damaged capacitors than the ECR.