Abstract
As critical dimensions (CD) of semiconductor devices continue to be scaled down, line width roughness (LWR), the looming critical index, needs to be well-controlled within 8% of gate line CD for advanced logic technology nodes as ITRS states. In this contribution, we investigated the impacts of different patterning schemes, post Barc-open treatment, process parameters in Barc (bottom anti-reflective coating) and Darc (Dielectric Anti-Reflect Coating) open steps on the post-etch LWR of poly-silicon gate. Results demonstrate the amorphous carbon based hard-mask approach outperforms other two typical patterning schemes. Post Barc-open treatment emerges as a feasible method. The effect of process parameters in Barc-open step highly depends on the specific gas combination and patterning scheme. LWR is insensitive to process parameters in amorphous carbon etch step.
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