Gate length dependence of bias temperature instability behavior in short channel SOI MOSFETs

Abstract

In this work, a comprehensive study of the bias temperature instability (BTI) degradation has been performed on SOI MOSFETs with various gate lengths (from 30nm to 150nm). For both nMOSFETs and pMOSFETs, the BTI degradation is alleviated when the gate length decreases. A new model was proposed to explain the observed gate length dependence of the BTI degradation. The decrease in the BTI degradation of MOSFETs with shorter gate length is caused by the decrease in normal electric field across the interface of Si-dielectric, which was concept-proofed by TCAD simulations.