Gate Length and Gate Width Dependence of Drain Induced Barrier Lowering and Current-Onset Voltage Variability in Bulk and Fully Depleted Silicon-on-Insulator Metal Oxide Semiconductor Field Effect Transistors

Abstract

This paper presents the statistical analysis of a newly found drain current variability component called “current-onset voltage” (COV) variability as well as drain induced barrier lowering (DIBL) variability in bulk and fully-depleted (FD) silicon-on-insulator (SOI) devices. Intensive variability measurement data show that gate length and gate width dependent COV variability and DIBL variability in bulk metal–oxide–semiconductor field effect transistors (MOSFETs) deviate from the straight line in the Pelgrom plot. On the other hand, COV variability and DIBL variability in FD SOI MOSFETs fall on the straight line. Their mechanisms are discussed based on three-dimensional (3D) device simulation considering random dopant fluctuation (RDF). It is found that the saturation of the COV and DIBL variability in smaller devices is caused by weaker averaging effect of channel potentials.