Gate leakage properties of MOS devices with tri-layer high- k gate dielectric

Abstract

Gate leakage of deep-submicron MOSFET with stack high- k dielectrics as gate insulator is studied by building a model of tunneling current. Validity of the model is checked when it is used for MOSFET with SiO 2 and high- k dielectric material as gate dielectrics, respectively, and simulated results exhibit good agreement with experimental data. The model is successfully used for a tri-layer gate-dielectric structure of HfON/HfO 2/HfSiON with a U-shape nitrogen profile and a like-Si/SiO 2 interface, which is proposed to solve the problems of boron diffusion into channel region and high interface-state density between Si and high- k dielectric. By using the model, the optimum structural parameters of the tri-layer dielectric can be determined. For example, for an equivalent oxide thickness of 2.0 nm, the tri-layer gate-dielectric MOS capacitor with 0.3-nm HfON, 0.5-nm HfO 2 and 1.2-nm HfSiON exhibits the lowest gate leakage.