Challenges and Performance Limitations of High-k and Oxynitride Dielectrics Materials for Low Power CMOS Applications

Abstract

For low power applications, the increase of gate leakage current, caused by direct tunneling in ultrathin oxide films, is the crucial factor eliminating conventional SiO2-based gate dielectrics in sub-90nm CMOS technology development. Recently, promising performance has been demonstrated for poly-Si/High-k and poly-Si/SiON gate stacks in addressing gate leakage requirements for low power applications. However, the use of poly-Si gate electrodes on high-k created additional issues such as channel mobility and reliability degradations, as well as Fermi level pinning of the effective gate work function. Therefore, oxynitride gate dielectrics are being proposed as an intermediate solution toward the sub-65nm/45nm nodes. Apparently an enhanced SiON gate dielectric stack was developed and reported to achieve high dielectric constant and good interfacial properties. The purpose of this paper is to provide a comprehensive review some of the device performance and limitation that High-k and oxynitride as dielectric materials are facing for sub-65nm/45nm node.