Gate insulation yield loss due to lattice misfit stress in MCT and IGBT devices

Abstract

An attempt was made to simplify the processing of MCT (MOS controlled thyristor) and IGBT (insulated-gate bipolar transistor) devices by combining the anneal of the p/sup +/-emitter with the gate oxidation process. A high-dose boron implantation prior to the gate oxidation is found to be responsible for significantly reduced breakdown field strengths observed for gate oxides in the MCT and IGBT devices. A failure mechanism based on lattice misfit stress and implantation damage below the amorphization threshold is proposed, which explains the observation that breakdown events occur exclusively at the very periphery of the implanted regions. This is in accordance with the scaling law that is found, exhibiting a logarithmic relationship between the breakdown strength of MOS capacitors and the perimeter length of p/sup +/ regions in the substrate. The substantial reduction in breakdown field strength was found to result in yield losses. By appropriate separate annealing of the p/sup +/-emitter, such weak spots in the gate oxide are not observed. With the use of BF/sub 2//sup +/ for the p/sup +/-emitter implantation it was possible to prevent yield losses and to reach intrinsic breakdown field strengths while still staying with the simplified device processing. >