Gate Influence on the Layout Sensitivity of $ \hbox{Si}_{1 - x}\hbox{Ge}_{x}\ \hbox{S/D}$ and $\hbox{Si}_{1 - y}\hbox{C}_{y}\ \hbox{S/D}$ Transistors Including an Analytical Model

Abstract

We present a simulation study on the effect of the gate module on the channel stress in Si1-xGex and Si1-yCy S/D MOS transistors. Stiff gate materials, such as titanium nitride, lead to a decreased channel stress, while a replacement-gate scheme allows the increase of the effectiveness of the Si1-xGex and Si1-yCy S/D techniques significantly, independent of the gate material used. The drawback of using a replacement gate is that the channel stress becomes more sensitive to layout variations. In terms of effect on Si1-xGex/Si1-yCy S/D stress generation, using a thin metal gate capped by polysilicon is similar to a full metal gate if the thin metal gate thickness exceeds 10 nm. Even metal gates as thin as 1 nm have a clear influence on the stress generation by Si1-xGex/Si1-yCy S/D. Removing and redepositing the polysilicon layer while leaving the underlying metal gate unchanged increases the stress, although not to the same extent as for complete gate removal. A simple analytical model that estimates the stress in nested short-channel Si1-xGex and Si1-yCy S/D transistors is presented. This model includes the effect of germanium/carbon concentration, active-area length, as well as the effect of gate length and the Young's modulus of the gate. Good qualitative agreement with 2-D finite element modeling is demonstrated.