Gate energy efficiency and negative capacitance in ferroelectric 2D/2D TFET from cryogenic to high temperatures

Sadegh Kamaei,Carlotta Gastaldi,Teodor Rosca,Matteo Cavalieri,Ali Saeidi,Adrian M Ionescu,Luca Capua

doi:10.1038/s41699-021-00257-6

Sadegh Kamaei, Carlotta Gastaldi + Show 5 more

Open Access

https://doi.org/10.1038/s41699-021-00257-6

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Abstract

We report the fabrication process and performance characterization of a fully integrated ferroelectric gate stack in a WSe2/SnSe2 Tunnel FETs (TFETs). The energy behavior of the gate stack during charging and discharging, together with the energy loss of a switching cycle and gate energy efficiency factor are experimentally extracted over a broad range of temperatures, from cryogenic temperature (77 K) up to 100 °C. The obtained results confirm that the linear polarizability is maintained over all the investigated range of temperature, being inversely proportional to the temperature T of the ferroelectric stack. We show that a lower-hysteresis behavior is a sine-qua-non condition for an improved energy efficiency, suggesting the high interest in a true NC operation regime. A pulsed measurement technique shows the possibility to achieve a hysteresis-free negative capacitance (NC) effect on ferroelectric 2D/2D TFETs. This enables sub-15 mV dec−1 point subthreshold slope, 20 mV dec−1 average swing over two decades of current, ION of the order of 100 nA µm−2 and ION/IOFF > 104 at Vd = 1 V. Moreover, an average swing smaller than 10 mV dec−1 over 1.5 decades of current is also obtained in a NC TFET with a hysteresis of 1 V. An analog current efficiency factor, up to 50 and 100 V−1, is achieved in hysteresis-free NC-TFETs. The reported results highlight that operating a ferroelectric gate stack steep slope switch in the NC may allow combined switching energy efficiency and low energy loss, in the hysteresis-free regime.

Highlights

The scaling of complementary metal-oxide-semiconductor (CMOS)is facing several fundamental and technical challenges due to the inability to remove the heat generated in the switching process[1].This results in jeopardizing the performance of aggressively scaled CMOS technology nodes[2,3]
Gate energy efficiency factor is defined to evaluate the gate control ability for the realization of steep slope if we carefully look at the dielectric susceptibility according to the Curie–Weiss law switches with negligible hysteresis loss
B Schematic diagram of the negative capacitance (NC) 2D/2D vdW vertical Tunneling field effect transistors (TFETs) in which 16 nm of Si:HfO2 is integrated into the gate stack (4-nm-thick Al2O3) of a back gated WSe2/SnSe2 heterojunction TFET. c SEM image of the fabricated device, showing WSe2 and SnSe2 flakes for the junction, the Pd contacts, and the overlapped tunneling region. d The crystal structure of Si:HfO2 in its two stable polarization states, which occurs due to the ionic movement. e The P − V and I − V curves of a 16-nm-thick Si:HfO2 ferroelectric capacitor, exhibiting a sharp and coherent switching

Summary

Introduction

The scaling of complementary metal-oxide-semiconductor (CMOS)is facing several fundamental and technical challenges due to the inability to remove the heat generated in the switching process[1].This results in jeopardizing the performance of aggressively scaled CMOS technology nodes[2,3]. The NC effect in 2D/2D TFETs is studied by evaluating the device performance at high temperatures, up to 100 °C, in both DC and pulsed measurement techniques.

Results

Conclusion