(Invited) Negative Capacitance Using Ferroelectrics for Future Steep-Slope MOSFETS

Abstract

Effective negative capacitance has been postulated in ferroelectrics because there is hysteresis in plots of polarization-electric field. In future integrated circuits, the incorporation of negative capacitance into MOSFET gate stacks would reduce the sub-threshold slope, enabling low power operation and reduced self-heating. As a step towards meeting this challenge, effective negative capacitance is demonstrated at room temperature in metal-insulator-metal capacitors, where it is stabilized by the presence of a paraelectric material. Steep slope MOSFETs are a priority research area, driven by the need for low energy CMOS. Gate capacitance places a lower limit on the sub-threshold slope. The consequence is that transistors need a larger applied voltage to be on and/or will leak current and so can never be fully switched off. This leads to increased power loss and heating as more transistors are crammed onto the same area of silicon, which limits component density. The concept of ferroelectrics displaying effective negative permittivity has led to the speculation that their inclusion in the gate stack of a MOSFET will reduce the sub-threshold swing, S, of CMOS devices below 60 mV/dec. For a gate stack comprising a thin ferroelectric layer on top of a thin SiO2 layer, the channel potential ψs can change more than the gate voltage Vg, thus providing a step-up voltage transformer and S < 60 mV/dec. If this can be engineered, it heralds a transformation of future integrated circuits (ICs), reducing the off-state current (Ioff) and/or supply voltage (VDD) which otherwise limits Moore’s Law as heat generated during switching cannot be removed. The idea has led to the search for unambiguous experimental evidence of negative capacitance in candidate ferroelectrics at room temperature as a step towards this ambition. In this study, experimental evidence is presented to demonstrate effective negative capacitance at room temperature in thin films of the ferroelectric BaTiO3. The BaTiO3 is fabricated in a bi-layer stack in series with SrTiO3, which is paraelectric at room temperature. The Metal-Insulator-Metal (MIM) stack is formed on a SrTiO3 substrate and using SrRuO3 as the bottom conducting electrode, which is lattice matched to the substrate. As the BaTiO3 layer thickness increases then the total capacitance is seen to increase, which is consistent with the ferroelectric capacitance being negative. In each case the bi-layer capacitance exceeds the SrTiO3 capacitance alone. Any hysteresis behavior is absent from the capacitance measurements in these bi-layer devices. The present work demonstrates the feasibility of negative capacitance at room temperature using a lead-free perovskite ferroelectric of varying thickness. The robust material can be integrated into CMOS or included as a performance booster within innovative devices such as tunnel field effect transistors in order to realize a future low power technology.