Gate edge roughness in electron beam direct write and its influence to device characteristics

Abstract

Line edge roughness (LER) and line width roughness (LWR) have raised questions and concerns as current lithography techniques reduce critical dimensions (CD) below 50 nm. There are few applications of controlled variation of LER and LWR, even among those which use electron beam direct writing (EBDW), although it is highly desirable to test the influence of systematical variation of LER and LWR on actual semiconductor devices. To get a clear understanding how and what the LERs and LWRs are influencing in EBDW, we have designed and fabricated transistor gates with programmed LER and LWR using EBDW and observed those based on CD-SEM metrology. The obtained results including calculated power spectrum density (PSD) shows the capability of EBDW to control the LER/LWR. Further, the influence of edge/width roughness in EBDW on device characteristics is reviewed and it gives how the effect of LWR/LER translates to device performance in DRAM process flow. It is found that the control of LWR is more important than that of LER for future lithography developments.