Gate-Drain Charge Analysis for Switching in Power Trench MOSFETs

Abstract

For the switching performance of low-voltage (LV) power MOSFETs, the gate-drain charge density (Q/sub gd/) is an important parameter. The so-called figure-of-merit, which is defined as the product of the specific on-resistance (R/sub ds,on/) and Q/sub gd/ is commonly used for quantifying the switching performance for a specified off-state breakdown voltage (BV/sub ds/). In this paper, we analyzed the switching behavior in power trench MOSFETs by using experiments and simulations, focusing on the charge density Q/sub gd/. The results of this analysis can be used for further optimization of these devices. The results show that the Q/sub d/ can be split into three charge contributions: accumulation, depletion, and inversion charge. It is shown that the inversion charge is located mainly underneath the trench bottom. The accumulation and depletion charge contribute each about 45% in conventional LV trench MOSFETs and can be reduced by using a thick bottom oxide in a shallow trench gate just extending in the drift region. Further, we derived an analytical model for calculating the Q/sub gd/, that takes into account the geometry dependence.