Gate Diffusion Input technique based full swing and scalable 1-bit hybrid Full Adder for high performance applications

Abstract

A full-swing high-speed hybrid Full Adder (FA) cell based on Gate Diffusion Input (GDI) technique and Conventional Complementary Metal-Oxide Semiconductor (CCMOS) logic has been proposed in this work. The design has been verified and compared with ten existing state-of-the-art FAs to validate its performance. Simulations were conducted using Cadence Computer Aided Design (CAD) tool in 45 nm CMOS process. The proposed design shows significant performance improvement in terms of speed and Power Delay Product (PDP). To evaluate performance parameters in large structures, the FAs have been cascaded and extended up to 32 bits. The proposed design, along with five out of ten existing designs worked flawlessly when extended to 32 bits. However, the proposed design achieved the best performance parameters in large cascaded circuits.