Gate Dielectric Treated by Self-Assembled Monolayers (SAMs) to Enhance the Performance of InSnZnO Thin-Film Transistors

Abstract

Self-assembled monolayer (SAM) treatment of gate dielectrics is a standard process for manufacturing organic thin-film transistors (TFTs) to reduce interface trap density and surface energy. However, it is rarely used for oxide semiconductor-based TFTs because the SAMs may be damaged during the manufacturing process. To explore the feasibility of using a SAM-treated gate dielectric to improve the performance of oxide TFTs, we study the effects of different SAM treatments of the gate dielectric layer on the performance of InSnZnO (ITZO) TFTs, which can help guide the selection of SAMs. After treatment with methyltriethoxysilane (C1-SAM), the performance of the TFTs is significantly improved, showing a drastic improvement in the ON/ OFF ratio and carrier mobility, and a reduction of the interface trap density and <inline-formula> <tex-math notation="LaTeX">${V}_{\text {th}}$ </tex-math></inline-formula> shift of the device under positive/negative bias stress (PBS/NBS). However, after treatment with n-octyltriethoxysilane (C8-SAM) and octadecyltriethoxysilane (C18-SAM), the performance of the TFTs deteriorate or even fail. Nevertheless, this work demonstrates an effective strategy for the construction of high-performance metal oxide TFTs, though it may require careful selection of the SAMs.