GaAs RISC processors

R.B Brown,A.I Kayssi,R.J Lomax,K.A Sakallah,A Chandna,P.J Sherhart,T.R Huff,R Uhlig,T.N Mudge,P Barker,M Upton,D Nagle

doi:10.1109/gaas.1992.247218

GaAs RISC processors

R.B Brown, A.I Kayssi + Show 10 more

https://doi.org/10.1109/gaas.1992.247218

Copy DOI

Publication Date: Oct 4, 1992

Citations: 7

Affiliation: University of Michigan–Ann Arbor

#Direct Coupled FET Logic #Reduced Instruction Set Computer + Show 8 more

Abstract
Full-Text
Similar Papers

Abstract

A simplified version of a RISC (reduced instruction set computer) microprocessor has been implemented with E/D MESFET DCFL (direct coupled FET logic) in the Vitesse HGaAs II process. This chip was designed to drive the development of digital GaAs design automation tools. The processor architecture was modified to fit DCFL technology. The 60,500-transistor circuit executes a set of 29 basic instructions. It dissipates 11 W and operates at over 100 MHz. >

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Similar Papers

Paper Title

Journal

Date

Author

View more papers

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.